Hyperstone Technology Overview

The unified Hyperstone RISC/DSP architecture

The Hyperstone RISC technology is based on a load-store architecture. It is register-oriented and build around a 32-Bit wide register stack that holds 64 general purpose local registers and 26 global registers. Load and store instructions are pipelined to a depth of 2 stages at the memory bus. The DSP unit also operates on the register set of the architecture in parallel to the ALU and load/store unit. It executes a dedicated DSP instruction set. Like the other instructions, the DSP instructions are strictly following the RISC-prinziples. During the latency cycles of DSP instructions the ALU and load/store unit can execute other instructions.

Thus, a much higher degree of flexibility is achieved compared to conventional DSP implementations. Additionally, up to three operations per clock cycle can be executed.
Therefore, a peak performance of up to 300 MOPS at 100 MHz can be achieved.

The Hyperstone RISC/DSP architecture has a set of totally 96 32-Bit registers, of which 64 are local registers and the others are global registers. The register stack is organized as a circular buffer and uses the concept of overlapping stack frames. Hyperstone RISC/DSP processors use variable length instructions with 16, 32 and 48-Bit instructions. Very useful are the integrated timers, the interrupt handler and the comprehensive bus interface for glueless connection of any kind of memory and peripherals. An automatic power-down mechanism further reduces the already low power consumption which is one result of the compact design.

On chip DSP Features for demanding multimedia and telecom applications

The DSP unit of the Hyperstone RISC/DSP is strictly following RISC principles. Like the ALU, all DSP instructions are working on the register set of the architecture, thus making data transfer between ALU and DSP transparent. The DSP unit gives support for 16-Bit and 32-Bit data types. In order to achieve highest data throughput the DSP unit provides dedicated result registers and a 32-Bit hardware accumulator as well as a 64-Bit hardware accumulator.

	Among the dedicated DSP-type instructions are
	16-Bit data format Multiply (single-cycle, pipelined) Multiply-accumulate Complex multiply Complex multiply-accumulate Addsub Fixed-point shift	2-bit data format Multiply Multiply-accumulat
	The whole DSP mechanism, including parallel execution of ALU, Load/Store unit and DSP is fully supported by Hyperstone’s DSP library hyDSP.