LatticeECP3 Evaluation

LatticeECP3 Serial Protocol Evaluation Board

The LatticeECP3 Serial Protocol Evaluation Board allows designers to investigate and experiment with the features of the LatticeECP3 high-speed SERDES transceivers. The board is available for full and detailed characterization of the high speed I/O channels and includes interfaces for some of the latest protocol interconnections.

LFE3-95EA-SP-EVN

Features

• PCI Express x4 edge connector
• Serial ATA interfaces
• RJ45 interface to 10/100/1000 Ethernet
• On-board Boot Flash
• 64M Serial SPI Flash
• Parallel Flash via MachXO™ Crossover PLD programming bridge
• Parallel Flash via MachXO™ Crossover PLD programming bridge
• DDR2 and DDR3 memory components
• Switches, LEDs, displays for demo purposes

• Several debug and analysis connections
• Input connection for lab-power supply
• Power connections and power sources
• ispVM™ programming support
• On-board and external reference clock sources

LatticeECP3 Video Protocol Evaluation Board

The LatticeECP3 Video Protocol Evaluation Board allows designers to investigate and experiment with different video protocols like DisplayPort, SMPTE standards (SD-SDI, HD-SDI and 3G-SDI) and DVB-ASI using up to 16 channels of embedded SERDES/PCS. 7:1 LVDS video interfaces like ChannelLink and CameraLink are also supported.

LFE3-95EA-V-EVN

Features

• Video interfaces for interconnection to video standard equipment
• High speed Mezzanine connector connected to SERDES channels
• On-board Boot Flash with Serial SPI Flash memory device
• Parallel Flash via MachXO™ Crossover PLD programming bridge
• SMAs for external high-speed clock / PLL inputs
• Switches, LEDs and LCD display header for demo purposes

• Mictor connector for using Logic Analyzer in the debugging phase
• Input connection for lab-power supply
• Power connections and power sources
• ispVM™ programming support
• On-board and external reference clock sources
• User-defined input and output points
• Performance monitoring via test headers, LEDs and switches

LatticeECP3 IO Protocol Evaluation Board

The LatticeECP3 IO Protocol Evaluation Board provides a convenient platform to evaluate, test and debug user designs and IP cores targeted for the LatticeECP3-95 FPGA. The LatticeECP3 I/Os are connected to a rich variety of both generic and application-specific interfaces.

LFE3-150EA-IO-EVN

Features

• On-board Boot Flash
• 2x 64 bit DDR3 DIMM module sockets
• Tri-speed Ethernet PHY with RJ-45
• USB 2.0 transceiver
• High-speed HM-Zd connector with 80 differential pair connections
• 8-pin DIP switch
• Discrete LEDs and 7-segment LED
• LCD module connector
• Prototyping areas with 96 IO pins
• Logic analyzer probe connection
• 2 pairs of high speed differential IO using SMA connectors

• 2 selectable high speed differential external clock sources with PLL feed back inputs
• 4 channels SERDES using SMA connectors
• 1 high current high speed IO connection using an SMA connector
• 3 fixed or adjustable DDR3 reference voltages
• ispVMTM programming support
• Multi-board JTAG programming capability and sysCONFIG connector