The LatticeECP2^TM (EConomy Plus 2nd generation) family redefines the low-costFPGA category. Features that the LatticeECP2 family brings to the low-cost FPGA category include high-performance DSP blocks, up to 70K LUT capacity, support for DDR1/2 memory interfaces at 400/533Mbps and up to 840Mbps generic LVDS performance. The LatticeECP2 also provides enhanced FPGA configuration options with features such as dual boot, bitstream encryption and TransFRTM I/O capability.

Key Features and Benefits

• Low Cost FPGAs
• Features optimized for mainstream applications
• Balanced logic-memory-I/O resources
• Extensive Density and Package Options
• 6K to 70K LUT4s, 95 to 583 I/O
• Density migration supported
• TQFP, PQFP and fpBGA packaging options
• Pb-free / RoHS-compliant options
• Embedded and Distributed Memory
• 12Kb to 136Kb distributed memory
• 55Kb to 1Mb block memory
• sysDSP™ High-Performance DSP Support up to 420MHz
• Multiply, accumulate,addition and subtraction
• Pipeline registers
• 12 to 88 multipliers (18 x 18)
• Flexible sysIO™ Buffers
• LVCMOS 33/25/18/15/12
• PCI
• SSTL3/2/18 & HSTL15 & HSTL18
• LVDS, RSDS, Bus-LVDS, MLVDS & LVPECL

• Pre-Engineered Source Synchronous I/O
• DDR1/2 (400/533Mbps)
• Generic (840Mbps)
• sysCLOCK™ PLL and DLL
• 2 DLLs per device
• 2 to 6 PLLs per device
• System Level Support
• IEEE 1149.1 boundary scan
• 1.2V power supply
• Enhanced Configuration
  Each LatticeECP2 device can be configured using:
• Low-Cost SPI Flash Memory
• LatticeECP2 JTAG Port
• LatticeECP2 Serial or Parallel Microprocessor Port
• Dual Boot Operation
  Supports the storage of multiple configurations in SPI memory
• Bitstream Encryption
  LatticeECP2S devices provide on-chip, non-volatile key storage to support decryption of a 128-bit AES encrypted bitstream
• TransFR™I/O
  Allows I/O states to be frozen during device configuration

Block structure of ECP2-20

Pre-Engineered Source Synchronous I/O
The I/O cells in the LatticeECP2/M devices contain a number of pre-engineered elements to allow the easy implementation of source synchronous interfaces such as those found on DDR1/2 memories,SPI4.2 systems and high-speed ADC/DACs.

• Precision DQS/Strobe Delay Control
• Dedicated DDR Registers (For Mux and Demuxing)
• Automatic DQS to System Clock Transfer
• 2:1 Gearbox Logic to Match I/O Speed with FPGA Fabric
• Low Skew Edge Clocks

Dual Boot Operation
Supports the storage of multiple configurations in SPI memory, adding flexibility and reliability, particularly for systems that require field updates.

Bitstream Encryption
LatticeECP2/M devices provide on-chip, non-volatile key storage to support decryption of a 128-bit AES encrypted bitstream, securing designs and preventing design piracy.

TransFR^TM I/O
LatticeECP2/M devices feature TransFR I/O that allows I/O states to be frozen during device configuration. This allows device field updates with a minimum of system downtime.